As means of digital modulation for the digital mobile communication, the .pi./4-shift QPSK method which carries out the modulation while shifting the phase axis by .pi./4at a time for each symbol period (two bits,for example) which forms one data unit has been adopted on account of various advantages attendant thereon, as discussed in "Proposal of Linear Modulation Method for Digital Mobile Communication," No. 2348, written jointly by Yoshihiko Akaiwa and Yoshiki Nagata and presented at the 1985 Consolidated National Meeting of Electronic Communication Society (Literature 1). The differential demodulator of the .pi./4-shift QPSK method which realizes miniaturization of the structure of modulation and economization of the power consumption has been also proposed in
"Proposal of Linear Modulation Method for Digital Mobile Communication," No. 2348, written jointly by Yoshihiko Akaiwa and Yoshiki Nagata and presented at the 1985 Consolidated National Meeting of Electronic Communication Society PA1 ".lambda./4-Shift QPSK Differential Demodulator for Digital Cordless Telephone," No. B-344, written Jointly by Hiroshi Shida, Tsutomu Suda, and Kenzo Urabe and presented at the 1992 Spring General Meeting of Electronic Data Communication Society (Literature 2).
FIG. 16 represents a block diagram of the conventional differential demodulator which is disclosed in literature 2.
Now, the differential demodulator for the modulation of a .pi./4-shift QPSK signal will be described below with reference to FIG. 16.
The differential demodulator comprises an input terminal 1, an oscillator 2, an instantaneous phase detecting circuit 3, a phase difference computing circuit 5, a clock recovery circuit 7, a data regenerating circuit 8, a clock recovery signal output terminal 9, and a regenerating data output terminal 10.
The input terminal 1 admits a modulation wave (carrier wave) signal (10 or 7 MHz, for example) which has been modulated by the .pi./4-shift QPSK method.
The oscillator 2 generates an electric oscillation which is asynchronous with and substantially equal in frequency to the modulated signal introduced to the input terminal 1.
FIG. 17 represents. a block diagram of the conventional instantaneous phase detecting circuit 3. The instantaneous phase detecting circuit 3 is composed of an exclusive OR (hereinafter "EX-OR") circuit 171, a D type flip-flop (hereinafter "DFF") circuit 172, an analog low-pass filter (hereinafter "LPF") 173, an analog/digital converter (hereinafter "A/D converter") 174, and a polarity switching circuit 175.
Now, the operation of the instantaneous phase detecting circuit 3 will be described below with reference to FIG. 18.
FIG. 18a represents phase detection characteristics which have been processed by the EX-OR circuit 171 and the LPF 173. In the diagram, the periods of 0-.pi., 2.pi.-3.pi., and 4.pi.-5.pi. have an upwardly slanting phase detection characteristic and the periods of .pi.-2.pi., 3.pi.-4.pi., and 5.pi.-6.pi. have a downwardly slanting phase detection characteristic respectively to the right. FIG. 18b represents the phase detection characteristics of the DFF circuit 172. In the diagram, the periods of 0-.pi., 2.pi.-3.pi., and 4.pi.-5.pi. have a phase detection characteristic of 1 and the periods of .pi.-2.pi., 3.pi.-4.pi., and 5.pi.-6.pi. have a phase detection characteristic of 0.
The output shown in FIG. 18a is emitted as it is when the output from the DFF circuit 172 is 1. The output shown in FIG. 18a is emitted with the sign thereof inverted when the output from the DFF circuit 172 is 0. As a result, a linear phase detection is effected over the periods of from .pi. to 3.pi. and 3.pi.to 5.pi. as shown in FIG. 18c.
The clock recovery circuit 7 is composed of a clock recovery signal generating circuit 71 and a digital phase locked loop (hereinafter "DPLL") 72 as shown in FIG. 19. The clock recovery signal generating circuit 71 is composed of a magnitude comparator 711 and a level setting circuit 712.
FIG. 20a represents the relation between the conventional clock recovery signal and the eye pattern. The term "eye pattern" refers to a figure derived from the loci of a phase difference signal 6 which are described by all the patterns possibly assumed by the phase difference signal 6. The expression "the eye pattern is opened" as used herein refers to the state in which figures enclosed with one phase difference signal 6 and another phase difference signal 6 assume the shape of a human eye. The expression "the eye pattern is closed" refers to the state in which figures enclosed with such phase difference signals 6 assume a decreased area.
The conventional instantaneous phase detecting circuit 3, however, relies for phase discrimination on the DFF circuit 172. The phase discrimination by the DFF circuit 172 lasts only during the instant of initiation of the signal admitted into the clock terminal. When the input modulation wave has a low frequency, namely when the frequency of the oscillator 2 is low (as, for example, when a frequency of 1.2 MHz is used), therefore, the intervals of polarity discrimination are too wide to coincide with the phase discrimination of FIG. 18a. The phase discrimination in this case, therefore, is at a disadvantage in breaking the continuity of the phase detection in the neighborhood of .pi., 2.pi., . . . , n.pi. (n for an integer).
Further, the conventional clock recovery signal generating circuit 71 entails jitters .+-..delta. as shown in FIG. 20b. Therefore, it has the problem of developing a deadlock and consequently failing to effect a recovery satisfactorily when the recovered clock signal by the DPLL 72 has a difference of 180.degree. from the phase of the phase difference signal 6. The term "jitters" as used herein refers to fluctuations of the phase difference signal 6 relative to the clock signal.
With reference to the diagram of FIG. 20a, the Jitters are substantially effaced by setting the detection level during the period of preamble at level 2 (phase difference of .pi./4) and returning the detection level to level 1 (phase difference of 0) after termination of the period of preamble. This method, however, entails the necessity of discerning whether the data currently received are those of preamble, those of UW, or those of data proper. The discrimination of sorts of data proves appreciably difficult and requires use of such an external circuit as a microprocessor and can never be realized by a simple circuit configuration. The external microprocessor is so busy in realizing other functions of processing that it cannot be easily utilized for discriminating between sorts of data. As a result, it is difficult to adopt the method which resorts to switching the set levels depending on the sorts of data mentioned above.
It is an object of this invention to provide an instantaneous phase detecting circuit which precludes discontinuation of phase and gives rise to no inconvenience in response to a decrease in the frequency of the input modulation wave. It is another object of this invention to provide an instantaneous phase detecting circuit which is composed of invariably digital circuits and has no use for the analog LPF 173 and the A/D converter 174 which have been heretofore found as indispensable components.
It is a further object of this invention to provide a clock recovery signal generating circuit which generates such a clock recovery signal as is capable of ideally effecting recovery at the time that the DPLL leads in a clock signal or even after it has led in the clock signal.